SAA7114H

Product Summary

The SAA7114H is a video capture device for applications at the image port of VGA controllers. The SAA7114H is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit. The applications of the SAA7114H include desktop video, multimedia, digital television, image processing, video phone applications.

Parametrics

SAA7114H absolute maximum ratings: (1)digital supply voltage, VDDD: -0.5 to +4.6V; (2)analog supply voltage, VDDA: -0.5 to +4.6V; (3)input voltage at analog inputs, VIA: -0.5 to VDDA + 0.5V; (4)output voltage at analog output, VOA: -0.5 to VDDA + 0.5V; (5)input voltage at digital inputs and outputs, outputs in 3-state;; (6)note 2, VID: -0.5 to +5.5 V; (7)output voltage at digital outputs, outputs active, VOD: -0.5 to VDDD + 0.5 V; (8)voltage difference between VSSAn and VSSDn, DVSS: 100 mV; (9)storage temperature, Tstg: -65 to +150℃; (10)operating ambient temperature, Tamb: 0 to 70℃; (11)operating ambient temperature under bias, Tamb(bias): -10 to +80 ℃; (12)electrostatic discharge all pins, note 3, Vesd: -2000 to +2000 V.

Features

SAA7114H features: (1)Six analog inputs, internal analog source selectors, e.g.; (2)6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS); (3)Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters; (4)Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel; (5)Automatic Clamp Control (ACC) for CVBS, Y and C; (6)Switchable white peak control; (7)Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the expansion port; (8)On-chip line-locked clock generation according“ITU 601”; (9)Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR; (10)Requires only one crystal (32.11 or 24.576 MHz) for all standards; (11)Horizontal and vertical sync detection; (12)Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards; (13)Luminance and chrominance signal processing for PAL BGDHIN, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM; (14)Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation: Increased luminance and chrominance bandwidth for all PAL and NTSC standardsp; Reduced cross colour and cross luminance artefacts; (15)PAL delay line for correcting PAL phase errors; (16)Independent Brightness Contrast Saturation (BCS) adjustment for decoder part; (17)User programmable sharpness control; (18)Independent gain and offset adjustment for raw data path.

Diagrams